When access to a memory is performed, in general, a virtual address issued by a processor is converted into a physical address and the converted physical address is used to access a cache memory or a main memory.
A process which converts a virtual address into a physical address is performed by a translation lookaside buffer (TLB). The access speed of the TLB has a great effect on the processing performance of a processor.
In general, the TLB is a high-speed SRAM. The SRAM is a volatile memory and data stored in the SRAM is erased when power is turned off. Therefore, in a case in which the TLB is formed by an SRAM, when power is turned on, a process of copying some of address conversion information from a page table to the TLB needs to be performed and it takes a lot of time until the TLB can be accessed, in addition, the memory size of the TLB is limited. Therefore, when a miss occurs in the TLB, it is necessary to acquire necessary address conversion information from the page table and it takes a lot of time to perform an address conversion process.
The processor accesses a cache memory before accessing a main memory. Therefore, there is a large difference between an access speed when data requested by the processor is stored in the cache memory and an access speed when the data is not stored in the cache memory. For this reason, in recent years, two or more levels of cache memories or a high-capacity cache memory has been provided to improve a cache hit rate.
However, in some cases, even when a high-capacity cache memory is provided, only a fraction of the cache memory is used and it is difficult to effectively use the high-capacity cache memory.